Encoding:

Format:

SUBQH[_R].PH 

SUBQH.PH     rd, rs, rt

SUBQH_R.PH   rd, rs, rt

Purpose:

Subtract Fractional Halfword Vectors And Shift Right to Halve Results

Element-wise fractional subtr action of halfword ve ctors, with aright shift by one bit to halve each result, with optional rounding.

Description:

rd = sign_extend(round((rs31..16 - rt31..16) >> 1) || round((rs15..0 - rt15..0) >> 1))

Each element from the two right-most halfword values in register rt is subtracted from the corresponding halfword element in register rs to create an interim 17-bit result.

In the non-rounding instruction variant, each interim result is then shifted right by one bit before being written to the corresponding halfword element of destination register rd.

In the rounding version of the instructi on, a value of 1 is added at the least- significant bit position of each interim result; the interim result is then right-shifted by one bit and written to the destination register.

This instruction does not modify the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDQH.PH:
   tempB15..0 = rightShift1SubQ16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = rightShift1SubQ16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
ADDQH_R.PH:
   tempB15..0 = roundRightShift1SubQ16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = roundRightShift1SubQ16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
function rightShift1SubQ16( a15..0 , b15..0 )
   temp16..0 = (( a15 || a15..0 ) - ( b15 || b15..0 ))
   return temp16..1
endfunction rightShift1SubQ16
function roundRightShift1SubQ16( a15..0 , b15..0 )
   temp16..0 = (( a15 || a15..0 ) - ( b15 || b15..0 ))
   temp16..0 = temp16..0 + 1
   return temp16..1
endfunction roundRightShift1SubQ16

Exceptions:

Reserved Instruction, DSP Disabled